Method of forming embedded capacitor structure applied to logic integrated circuit

ABSTRACT

A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a vertical three-dimensionalMIM capacitor structure (metal-insulator-metal capacitor structure), andmore particularly to a method for fabricating a verticalthree-dimensional metal-insulator-metal capacitor (MIM Capacitor)structure that is compatible with the fabrication process of a copperdual damascene in logic integrated circuit and integration for copperdual damascene process.

2. Description of the Prior Art

Precision capacitors for complementary metal oxide semiconductor (CMOS)analog applications are generally metal-insulator metal (MIM) capacitoror polysilicon-insulator-polysilicon (PIP) capacitors.

However, PIP capacitors are becoming less popular because they present anumber of problems when used with complementary metal oxidesemiconductor (CMOS) technologies. More specifically, PIP capacitors aregenerally performed before the CMOS structures and the heat andoxidation cycles that occur during the CMOS production process degradethe PIP capacitors. Further, the sophistication of analog circuits isimproving which requires that the variation in the capacitance bedecreased and preferably maintained at a voltage of approximately 25ppM. However, PIP capacitors suffer from carrier depletion that changesthe capacitance as surface voltage across the PIP capacitor changes.Therefore, PIP capacitors do mot maintain the linearly required intoday's sophisticated analog circuits. Further, PIP capacitors oftentrap charge within the insulator during their use.

Therefore, MIM capacitors, which are usually formed after the CMOSproduction process, are generally becoming more popular for analogcircuits. However, MIM capacitors also present manufacturing problems.More specifically, conventional MIM capacitors with a SiO₂ insulatorcannot be used over copper damascene metal wiring because copperdiffuses through the capacitor structure and create leakage current. Inother words, the copper is not a good electrode in the conventionalcapacitor structures. Therefore, conventional MIM capacitors aregenerally only used with aluminum wiring. This is a substantialdisadvantage because copper dual damascene wiring is becoming popular inCMOS technologies because copper is less expensive and has betterconductivity and electromigration resistance when compared to aluminumwiring. Therefore, there is a need for a process and structure thatallow MIM capacitors to be used with copper dual damascene wiring.

In the present semiconductor mix mode integrated circuits process, theplate capacitor structure such as MIM capacitor as. showed in the FIG.1. The traditional plate MIM capacitor structure may includes a firstmetal line M_(x) 102 is embedded within the substrate 100, whereinsubscript x represents the xth metal layer. The plate MIM capacitorstructure may also include a first plate (bottom plate) 104 on thesubstrate 100, a first dielectric layer (bottom dielectric layer) 106 onthe first plate 104, a top plate (second plate) 108 on the firstdielectric layer 106, and a second plate dielectric (top platedielectric) 110 on the second plate 108. The second metal line M_(x+1)112 contacts the exposed portion of the first metal line M_(x) 102,wherein the subscript x+1 represents x+1th metal layer. In thetraditional plate MIM capacitor structure, the plate MIM capacitorrequires a large chip area to satisfy the designed capacitance. Further,the traditional plate MIM capacitor requires three extra photo-mask todefine the first plate 104, dielectric layer 106, and second plate 108,respectively and the process is difficult to be comparable with thecopper dual damascene interconnect manufacturing flow.

SUMMARY OF THE INVENTION

In accordance with the present invention, a structure and a method isprovided for forming a vertical three-dimensional metal-insulator-metalcapacitor (MIM capacitor) on the substrate in logic integrated circuitand integration for copper dual damascene process, which is compatiblewith a copper dual damascene fabrication process, that substantiallydiminish the area of MIM capacitor at identical capacitance in logicintegrated circuit.

It is one object of this invention is to provide a structure of avertical three-dimensional MIM capacitor on the substrate that candiminish the space structure on the chip in logic integrated circuit.

It is another object of this invention is to provide a verticalthree-dimensional MIM capacitor structure on the substrate to increasethe capacitance density in logic integrated circuit.

It is a further object of this invention is to decrease the fabricatingsteps during the fabricating the vertical three-dimensional MIMcapacitor structure.

It is still an object of this invention is to fabricate the verticalthree-dimensional MIM capacitor structure with high capacitance densitythat the fabricating process is compatible with the copper dualdamascene wiring process.

According to above-mention, an embedded capacitor applied to logicintegrated circuit, such as a vertical three-dimensional MIM capacitorstructure may be formed on a substrate, wherein the substrate having aremaining hard mask layer and a portion of the prior metal line therein.Herein, the portion of the prior metal line is used as a first metalelectrode plate of the vertical three-dimensional MIM capacitorstructure. The vertical three-dimensional MIM capacitor structureaccording to the present invention may include a second metal electrodeplate that electrically coupled the first metal electrode plate by usinga middle contact structure, wherein said middle contact structure onsaid first metal electrode plate being exposed on substrate. In themeanwhile, a copper dual damascene structure adjacent the verticalthree-dimensional MIM capacitor structure on the substrate, and alsoelectrically coupled the prior metal line being exposed on substrate.Due to the MIM capacitor structure is a vertical three-dimensionalstructure such that the requiring structure space of the capacitorstructure on the chip can be diminished in the logic integrated circuit.

The process for forming a vertical three-dimensional MIM capacitorstructure is compatible with a copper dual damascene structurefabrication process. The method for forming the verticalthree-dimensional MIM capacitor is according to the present inventionmay include sequentially formed a first cap layer, a first dielectriclayer, and a first hard mask layer on the substrate. Then, a via openingand a trench opening of the first layer of the copper dual damascenestructure and the middle structure of the vertical three-dimensional MIMcapacitor are formed simultaneously by using two photolithographyprocesses, wherein the middle contact structure is used to electricallycouple the first metal electrode plate. Next, a first copper layer isdeposited to fill with the via opening and trench opening to form afirst layer of the copper dual damascene structure, and the portionstructure of the middle contact structure. Then, a second cap layer isformed on the above structure. Next, a third photoresist layer iscovered on the copper dual damascene structure to form an opening of themiddle contact structure. After the third photoresist layer is removed,a blanket insulator layer is deposited on the second cap layer that isnot removed and on the sidewall of opening of the middle contactstructure. Then, a second copper layer is deposited to fill with in theopening of the middle contact structure to form an inverse U-typecontact, and the excess second copper layer is planarized by polishingprocess. Thereafter, a second dielectric layer and a second hard masklayer are sequentially formed on the structure of abovementioned afterthe second copper layer is planarized. Then, a second metal electrodeplate and a second layer of the copper dual damascene structure (secondmetal electrode plate of the vertical three-dimensional MIM capacitorstructure) are defined simultaneously by using conventional copper dualdamascene techniques. Next, a third cap layer is formed on the abovestructure. Therefore, due to the fabrication of the verticalthree-dimensional MIM capacitor is compatible with the fabricating thecopper dual damascene structure process such that the number of thephoto-mask can be diminished during the fabricating the verticalthree-dimensional MIM capacitor structure.

Other objects, advantages and salient features of the invention willbecome apparent from the following detailed description taken inconjunction with the annexed drawings, which disclosed preferredembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is schematic representation of structures at various stagesduring the formulation of a traditional plate metal-insulator-metalcapacitor (MIM capacitor) structure using conventional, prior arttechnique;

FIG. 2 to FIG. 4 is schematic representations for forming a middlecontact structure of the vertical three-dimensional MIM capacitorstructure) within a first dielectric layer, and a first layer of thecopper dual damascene structure on the substrate simultaneously;

FIG. 5 to FIG. 8 are schematic representations of structures at variousstages during the formulation of the second layer of the copper dualdamascene structure, and the middle contact structure of a verticalthree-dimensional MIM capacitor to electrically couple the first metalelectrode plate in accordance with a method disclosed; and

FIG. 9 to FIG. 10 is schematic representations of structures at variousstages during the formulation of the vertical three-dimensional MIMcapacitor is compatible with the copper dual damascene structure inaccordance with a method disclosed herein.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Some sample embodiments of the invention will now be described ingreater detail. Nevertheless, it should be recognized that the presentinvention can be practiced in a wide range of other embodiments besidesthose explicitly described, and the scope of the present invention isexpressly not limited except as specified in the accompanying claims.

According to the present invention is to provide a mix mode logicintegrated circuit device comprises a vertical three-dimensional MIMcapacitor structure and a copper dual damascene structure aresimultaneously on the substrate, wherein the substrate having a priormetal line and a remaining hard mask layer are embedded in thesubstrate. One of the embodiments for the present invention, the portionof the prior metal line used as a first metal electrode plate of thevertical three-dimensional MIM capacitor structure. Another portion ofthe prior metal line is electrically coupled the copper dual damascenestructure.

The structure of the vertical three-dimensional MIM capacitor structuremay include a middle contact structure within a first dielectric layerthat is between the first metal electrode plate and second metalelectrode plate, and used to electrically couple the first and secondmetal electrode plates. The middle contact structure may include acontact on the first metal line being exposed on the substrate, and ablanket insulator layer on the sidewall of the contact to raise thecapacitance of the capacitor structure, The middle contact structurealso may include an inverse U-type contact on the insulator layer. Thesecond metal electrode plate of the vertical three-dimensional MIMcapacitor structure may include a metal layer on the middle contactstructure and within a second dielectric layer. Accordingly, thevertical three-dimensional MIM capacitor structure are constituted fromthe first metal electrode plate, middle contact structure, and secondmetal electrode plate, such that the space structure of capacitor can bediminished and the capacitance density can be raised.

Moreover, according to one of the embodiment of the present invention,the fabrication of the vertical three-dimensional MIM capacitorstructure is compatible with the copper dual damascene fabricatingprocess on the substrate, such that the space of the verticalthree-dimensional MIM capacitor structure which is smaller than theprior plate MIM capacitor structure defined on the chip.

Referring to FIG. 2, a first cap layer 14 is deposited on the substrate10, wherein the substrate 10 having a prior metal line 12 which is usedas a first metal electrode plate of the vertical three-dimensionalmetal-insulator-metal capacitor (MIM capacitor) structure and aremaining hard mask layer 14 are embedded within the substrate 10. Thematerial of the first cap layer 14 can be SiN (silicon nitride) or SiC(Silicon Carbide). Then, a first dielectric layer 18 and a first hardmask layer 20 with thickness between 100 to 1000 Å are sequentiallyformed on the first cap layer 16. The material of the first dielectriclayer 18 can be SiO₂, FSG, low dielectric constant (low-k) layer, orultra low k dielectric layer. Furthermore, due to the above material ofthe dielectric layer such as FSG and some CVD low-k dielectric materialcan be polished by CMP (chemical mechanical polishing) process and theproperties of the dielectric material will not be changed while thedielectric material contacts the CMP solution, such that the hard masklayer will not be used as a stop layer in polishing process. Therefore,the hard mask layer can be an optional process during fabricating thevertical three-dimensional MIM capacitor layer.

Next, referring to FIG. 3 and FIG. 4, there are two photolithographyprocesses on the first cap layer 16 to form a first via opening 24 and afirst trench opening 22 of a copper dual damascene structure, and anopening 26 of the middle contact structure of the verticalthree-dimensional MIM capacitor. In the FIG. 4, a first liner layer 28is deposited on the sidewall of the first trench 22 and the first via 24of the copper dual damascene structure and the opening 26 of the middlecontact structure of the vertical three-dimensional MIM capacitorstructure to prevent the metal layer such as copper in the trench or viawill be diffused into the dielectric layer to cause the breakdown orleakage current issue of the electronic device. Then, the first coppermetal layer is deposited to fill with the first trench opening 22 andthe first via opening 24 of the copper dual damascene structure and theopening 26 of the middle contact structure of the verticalthree-dimensional MIM capacitor to form a contact 30 within the firsthard mask layer 20 and the first dielectric layer 18, wherein thecontact 30 is electrically coupled the first metal electrode plate 12.Then, the excess the first copper metal layer and the first liner layer28 are planarized by first polishing process and stop on the first hardmask layer 20, wherein the first hard mask layer 20 is used as a stoplayer for first polishing process. Next, a second cap layer 34 is formedon the structure of the abovementioned.

Thereafter, referring to FIG. 5, a third photoresist layer 40 is formedcover the portion of the structure of FIG. 4. Then, the portion of thesecond cap layer 34, first hard mask layer 20, and a first dielectriclayer 18 are sequentially removed by an etching process to form aninverse U-type opening 44 of the middle contact structure. Next,referring to FIG. 6, a blanket insulator layer 46 is deposited on thesecond cap layer 34, and the sidewall of the inverse U-type opening 44of the middle contact structure of the vertical three-dimensional MIMcapacitor after the remaining third photoresist layer 40 is removed. Thematerial of the insulator layer 46 can be an oxide or a SiN. Thepreferable material of the insulator layer 46 for the present inventioncan be a high dielectric constant layer. The high dielectric constantlayer has a higher coupling ratio that can raise the capacitance densityof the capacitor structure. The material of the high dielectric constantlayer can be Ta₂O₅, Al₂O₃, or BSTO (barium strontium titanium oxide).

Then, referring to FIG. 7, the second liner layer 48 is formed on theblanket insulator layer 46 and the sidewall of the inverse U-typeopening 44 of the middle contact structure of the verticalthree-dimensional MIM capacitor by a PVD method (physical vapordeposition method) or a CVD method (chemical vapor deposition method).Then, a second copper metal layer 50 is electroplated to fill with theinverse U-type opening 44 of the middle contact structure to form aninverse U-type contact 52 within the first dielectric layer 18. Then,the excess second metal layer 50 on the second liner layer 48 isplanarized by second polishing process (chemical mechanical polishingprocess) and stop on the second liner layer 48 as shown in FIG. 8.

Thereafter, referring to FIG. 9, the second dielectric layer 54 isformed on the structure of the FIG. 8, and a second hard mask layer 56is deposited on the second dielectric layer 54. Then, the second metalelectrode plate of the vertical three-dimensional MIM capacitor and thesecond layer of the copper dual damascene structure are defined by aconventional copper dual damascene structure technique as shown in FIG.10. Next, the third metal layer is deposited to fill with the secondlayer 60 of the copper dual damascene structure, and the second layer ofa vertical three-dimensional MIM capacitor to form a second metalelectrode plate 58. Thereafter, the third cap layer 62 is deposited onthe above structure after second CMP process to polish the excess thirdmetal layer and stop on the second hard mask layer 56.

According to abovementioned, we can achieve the advantages as following:

Firstly, according to the capacitor structure of the present inventionis provided a vertical three-dimensional MIM capacitor structure on thesubstrate to diminish the space structure on the chip and raise thecapacitance density of the capacitor structure in the logic integratedcircuit.

Secondly, according to the steps for forming the structure of thevertical three-dimensional MIM capacitor of FIG. 2 to FIG. 9, thevertical three-dimensional MIM capacitor structure is compatible withthe copper dual damascene structure techniques such that the fabricatingsteps can be simplified.

Thirdly, according to FIG. 2 to FIG. 9, the second metal electrode plateand the second layer of the copper dual damascene structure are definedsimultaneously, such that the fabricating the vertical three-dimensionalMIM capacitor has an extra photomask and the fabricating process iscomparable with defining the copper dual damascene structure.

Although specific embodiments have been illustrated and described, itwill be obvious to those skilled in the art that various modificationsmay be made without departing from what is intended to be limited solelyby the appended claims.

What is claimed is:
 1. A method for fabricating a verticalthree-dimensional capacitor structure integrated with a damascenestructure, said method comprising steps of: providing a substrate;forming a first dielectric layer on said substrate; forming a first viaopening and first trench opening of said damascene structure, and afirst opening within said first dielectric layer on said substratesimultaneously by using a photolithography processes; depositing a firstcopper metal layer to fill with said first via opening and said firsttrench opening of said damascene structure to form a first layer of saiddamascene structure, and on said first opening to form a first contact;forming a photoresist layer cover said damascene structure; etching saidfirst dielectric layer to form an inverse U-type opening; removing saidphotoresist layer; depositing a blanket insulator layer on sidewall ofsaid inverse U-type opening; forming a second copper metal layer to fillwith said inverse U-type opening; planarizing said second copper metallayer to form an inverse U-type contact; depositing a second dielectriclayer on the portion of said inverse U-type contact and on saiddamascene structure; and forming a second layer of said damascenestructure and a second metal electrode plate on said inverse U-typecontact simultaneously.
 2. The method according to claim 1, whereinmaterial of said dielectric layer can be a low dielectric constantlayer.
 3. The method according to claim 1, wherein the material of saidblanket insulator layer can be a high dielectric constant layer.
 4. Themethod according to claim 3, wherein said high dielectric constant layeris selected from the group consisting of Ta₂O₅, Al₂O₃, and BSTO.
 5. Themethod according to claim 1, wherein said step of forming said secondcopper layer comprises an electroplating method.
 6. The method accordingto claim 1, wherein said step of forming said second layer of saiddamascene structure and forming said second metal electrode plate can bethe same fabricating process.